{"blog_title":"Vengineer\u306e\u5984\u60f3","blog_url":"https://vengineer.hatenablog.com/","published":"2012-04-24 06:16:09","title":"UVM\u3068Verilog-AMS","author_name":"Vengineer","type":"rich","provider_url":"https://hatena.blog","provider_name":"Hatena Blog","description":"Verification Evangelist\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f Synopsys\u306e\u30d6\u30ed\u30b0\uff1aUVM-based random verification using CustomSim-VCS for Analog Mixed Signal Designs\u3067\u306f\u3001CustomSim-VCS\u306b\u3088\u308bAnalog/Mixed-Signal Design and Verfication\u3067\u3059\u3002 VCS\u306f\u77e5\u3063\u3066\u3044\u307e\u3059\u304c\u3001CustomSim\u3063\u3066\u4f55\uff1f Google\u304f\u3093\u306b\u805e\u3044\u3066\u307f\u307e\u3057\u305f\u30023\u5e74\u524d\u306b\u30ea\u30ea\u30fc\u30b9\u3055\u308c\u3066\u3044\u305f\u2026","width":"100%","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F66405600\" title=\"UVM\u3068Verilog-AMS - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","height":"190","version":"1.0","categories":["UVM","#\u6280\u8853\u8077"],"image_url":null,"author_url":"https://blog.hatena.ne.jp/Vengineer/","url":"https://vengineer.hatenablog.com/entry/66405600"}