{"blog_url":"https://vengineer.hatenablog.com/","type":"rich","width":"100%","provider_url":"https://hatena.blog","url":"https://vengineer.hatenablog.com/entry/67160944","version":"1.0","title":"\u30b1\u30a4\u30c7\u30f3\u30b9\u306e\u691c\u8a3c\u95a2\u9023\u30a6\u30a7\u30d6\u30bb\u30df\u30ca\u30fc\u3044\u308d\u3044\u308d","description":"Verification Evangelist\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f 2nd Half Functional Verification Webinar Series\u3067\u306f\u3001\u30b1\u30a4\u30c7\u30f3\u30b9\u306e\u30c4\u30fc\u30eb\u3092\u5229\u7528\u3057\u305f\u5185\u5bb9\u306e\u30a6\u30a7\u30d6\u30bb\u30df\u30ca\u30fc\u304c\u305f\u304f\u3055\u3093\u3042\u308a\u307e\u3059\u3002 121025: UVM SystemVerilog in a Multi-Language SoC World 121113: UVM Sequences: Best Practices for Efficiency and Reuse 121127: Sim\u2026","author_url":"https://blog.hatena.ne.jp/Vengineer/","author_name":"Vengineer","image_url":null,"html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F67160944\" title=\"\u30b1\u30a4\u30c7\u30f3\u30b9\u306e\u691c\u8a3c\u95a2\u9023\u30a6\u30a7\u30d6\u30bb\u30df\u30ca\u30fc\u3044\u308d\u3044\u308d - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","provider_name":"Hatena Blog","height":"190","blog_title":"Vengineer\u306e\u5984\u60f3","categories":["Cadence","#\u6280\u8853\u8077"],"published":"2012-10-24 05:58:48"}