{"type":"rich","author_url":"https://blog.hatena.ne.jp/Vengineer/","url":"https://vengineer.hatenablog.com/entry/69928186","description":"@Vengineer\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f \u6628\u65e5\u306f\u3001ModelSim-AE\u306e\u3053\u3068\u3067\u3057\u305f\u304c\u3001\u4eca\u65e5\u306fModelSim-ME\u3002 \u3048\u3001ME\u3063\u3066\u306a\u3093\u3060\uff1f MicroSemi\u306b\u8cb7\u53ce\u3055\u308c\u305fActel\u7528\u306eModelSim\u3067\u3059\u3002 Libero SoC/Libero IDE\u306e\u30d1\u30c3\u30b1\u30fc\u30b8\u306b\u5165\u3063\u3066\u3044\u307e\u3059\u3002 \u6700\u65b0\u30d0\u30fc\u30b8\u30e7\u30f3\u306f\u300110.4b\u306e\u3088\u3046\u3067\u3059\u3002 \u3044\u3064\u306e\u9593\u306b\u304b\u3001VHDL OSVVM \u304c\u30d1\u30c3\u30b1\u30fc\u30b8\u306b\u306f\u5165\u3063\u3066\u3044\u307e\u3059\u3002 \u691c\u8a3c\u3001Verification\u3001SystemVerilog","version":"1.0","image_url":null,"blog_title":"Vengineer\u306e\u5984\u60f3","published":"2015-06-30 05:20:00","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F69928186\" title=\"ModelSim-ME - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","provider_name":"Hatena Blog","categories":["SystemVerilog","#\u6280\u8853\u8077"],"title":"ModelSim-ME","width":"100%","height":"190","provider_url":"https://hatena.blog","author_name":"Vengineer","blog_url":"https://vengineer.hatenablog.com/"}