{"version":"1.0","title":"UVM\u304cIEEE P1800.2\u306b","author_name":"Vengineer","author_url":"https://blog.hatena.ne.jp/Vengineer/","provider_url":"https://hatena.blog","description":"@Vengineer\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f \u4e45\u3057\u3076\u308a\u306b\u3001UVM\u306e\u304a\u8a71\u3002 UVM\u306eIEEE\u3067\u306e\u6a19\u6e96\u5316\u304c\u9032\u3093\u3067\u3044\u307e\u3059\u3002P1800.2\u306b\u306a\u308a\u307e\u3057\u305f\u3002 \u3053\u3061\u3089\u306b\u3088\u308b\u3068\u3001 P1800.2 - Standard for Universal Verification Methodology Language Reference Manual \u306b\u306a\u308b\u3088\u3046\u3067\u3059\u3002 UVM\u3068\u3044\u3046\u540d\u79f0\u306f\u6b8b\u308b\u306e\u3067\u3059\u306d\u3002 UVM 1.2\u6b63\u5f0f\u30ea\u30ea\u30fc\u30b9\u304b\u30891\u5e74\u3002 \u30e1\u30bd\u30c9\u30ed\u30b8\u8ad6\u4e89\u3082\u3084\u3063\u3068\u5b8c\u5168\u7d42\u7d50\u3067\u3059\u306d\u3002 Verification 4.0\u3067\u66f8\u3044\u305f\u2026","url":"https://vengineer.hatenablog.com/entry/70007595","provider_name":"Hatena Blog","height":"190","blog_title":"Vengineer\u306e\u5984\u60f3","image_url":null,"type":"rich","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F70007595\" title=\"UVM\u304cIEEE P1800.2\u306b - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","categories":["UVM","#\u6280\u8853\u8077"],"blog_url":"https://vengineer.hatenablog.com/","published":"2015-08-05 05:20:00","width":"100%"}