{"blog_url":"https://vengineer.hatenablog.com/","published":"2016-01-07 05:00:00","author_name":"Vengineer","provider_name":"Hatena Blog","version":"1.0","image_url":null,"html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F70319125\" title=\"\u6d41\u884c\u306eFPGA\u3068\u9ad8\u4f4d\u5408\u6210\u30b3\u30f3\u30d1\u30a4\u30e9\u3067\u81ea\u5206\u3060\u3051\u306e\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u3092\u4f5c\u3063\u3066\u307f\u3088\u3046 - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","provider_url":"https://hatena.blog","height":"190","width":"100%","blog_title":"Vengineer\u306e\u5984\u60f3","description":"@Vengineer\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f \u5948\u826f\u5148\u7aef\u79d1\u5b66\u6280\u8853\u5927\u5b66\u9662\u5927\u5b66 \u60c5\u5831\u79d1\u5b66\u7814\u7a76\u79d1\u304c2016\u5e742\u670825\u65e5\u300126\u65e5\u306b\u30b9\u30d7\u30ea\u30f3\u30b0\u30bb\u30df\u30ca\u30fc\u3092\u884c\u3046\u3088\u3046\u3067\u3059\u3002NAIST\u306e\u53d7\u9a13\u3092\u771f\u5263\u306b\u8003\u3048\u3066\u3044\u308b\u5927\u5b66\u751f\u4ee5\u4e0a (\u9ad8\u5c024\u5e74\u4ee5\u4e0a\u3001\u793e\u4f1a\u4eba\u3082\u542b\u3080)\u3092\u5bfe\u8c61\u3068\u3057\u3066\u3044\u308b\u3088\u3046\u3067\u3059\u3002 \u305d\u306e\u4e2d\u3067\u3001 \u5f15\u7528 \u6d41\u884c\u306eFPGA\u3068\u9ad8\u4f4d\u5408\u6210\u30b3\u30f3\u30d1\u30a4\u30e9\u3067\u81ea\u5206\u3060\u3051\u306e\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u3092\u4f5c\u3063\u3066\u307f\u3088\u3046 \u56de\u8def\u306e\u69cb\u6210\u3092\u5404\u81ea\u304c\u30ab\u30b9\u30bf\u30de\u30a4\u30ba\u3059\u308b\u3053\u3068\u304c\u3067\u304d\u308b\u67d4\u3089\u304b\u3044\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u306eFPGA\u304c\u3001\u7d44\u307f\u8fbc\u307f\u30b7\u30b9\u30c6\u30e0\u304b\u3089\u30c7\u30fc\u30bf\u30bb\u30f3\u30bf\u30fc\u307e\u3067\u3001\u5e45\u5e83\u3044\u5fdc\u7528\u3067\u6d41\u884c\u3057\u3066\u3044\u307e\u3059\u3002\u8fd1\u5e74\u2026","author_url":"https://blog.hatena.ne.jp/Vengineer/","title":"\u6d41\u884c\u306eFPGA\u3068\u9ad8\u4f4d\u5408\u6210\u30b3\u30f3\u30d1\u30a4\u30e9\u3067\u81ea\u5206\u3060\u3051\u306e\u30cf\u30fc\u30c9\u30a6\u30a7\u30a2\u3092\u4f5c\u3063\u3066\u307f\u3088\u3046","categories":["HLS","#\u6280\u8853\u8077"],"url":"https://vengineer.hatenablog.com/entry/70319125","type":"rich"}