{"title":"Portable Stimulus","blog_url":"https://vengineer.hatenablog.com/","width":"100%","version":"1.0","blog_title":"Vengineer\u306e\u5984\u60f3","provider_url":"https://hatena.blog","description":"@Vengineer\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f \u4eca\u5e74\u306eDVCon\u306f\u3001\u3069\u3046\u3084\u3089Portable Stimulus\u304b\u306a\u3002 Accellera\u3067\u306f\u3001\"Portable Stimulus\" Proposed Working Group\u3068\u3057\u30662014\u5e745\u6708\u304b\u3089\u6d3b\u52d5\u3092\u958b\u59cb\u3002 \u4e00\u3064\u306eSTIMULUS\u304b\u3089 \u30fbUML/SysML\u3001SystemC\u3001HVL/UVM(SV,e)\u3001C/C++\u3001AMS \u30fbSIMULATION\u3001EMULATION\u3001FPGA PROTO \u30fbIP BLOCK\u3001SUBSYSTEM\u3001FULL SYSTE\u2026","type":"rich","published":"2016-03-17 05:00:00","author_url":"https://blog.hatena.ne.jp/Vengineer/","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F70446847\" title=\"Portable Stimulus - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","url":"https://vengineer.hatenablog.com/entry/70446847","image_url":null,"author_name":"Vengineer","height":"190","provider_name":"Hatena Blog","categories":["SystemVerilog","#\u6280\u8853\u8077"]}