{"blog_title":"Vengineer\u306e\u5984\u60f3","height":"190","version":"1.0","url":"https://vengineer.hatenablog.com/entry/70446872","published":"2016-03-18 05:00:00","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F70446872\" title=\"MAX 10 NEEK - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","blog_url":"https://vengineer.hatenablog.com/","categories":["FPGA","#\u6280\u8853\u8077"],"title":"MAX 10 NEEK","author_url":"https://blog.hatena.ne.jp/Vengineer/","image_url":null,"provider_name":"Hatena Blog","author_name":"Vengineer","type":"rich","width":"100%","description":"@Vengineer\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f MAX 10 FPGA\u3067\u5b66\u3076FPGA\u958b\u767a\u5165\u9580\uff088\uff09 \u5468\u8fba\u6a5f\u5668\u306e\u5145\u5b9f\u3057\u305f\u300cMAX 10 NEEK\u300d\u3067\u672c\u683c\u7684\u306a\u958b\u767a\u3092\u76ee\u6307\u3059 \u3067\u7d39\u4ecb\u3055\u308c\u3066\u3044\u308bhttp://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=956#http://www.terasic.com.tw/attachment/archive/956/image/auto.jpg\u3063\u3066\u3001\u672c\u4f53\u306f359\u30c9\u30eb\u3067\u3001IP\u306f995\u30c9\u30eb\u306a\u306e\u2026","provider_url":"https://hatena.blog"}