{"type":"rich","description":"@Vengineer\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f \u5168\u90e8\u3001\u30e1\u30f3\u30bf\u30fc\u3067\u3059\u3002 Parameters, UVM, Coverage & Emulation \u2013 Take Two and Call Me in the Morning No RTL Yet? No Problem UVM Testing a SystemVerilog Fabric Model Whose fault is it? Advanced techniques for optimizing ISO 26262 fault analysi\u2026","image_url":null,"title":"UVM\u3067\u3044\u308d\u3044\u308d","categories":["UVM","#\u6280\u8853\u8077"],"url":"https://vengineer.hatenablog.com/entry/70472381","version":"1.0","provider_url":"https://hatena.blog","blog_url":"https://vengineer.hatenablog.com/","provider_name":"Hatena Blog","blog_title":"Vengineer\u306e\u5984\u60f3","height":"190","author_name":"Vengineer","width":"100%","author_url":"https://blog.hatena.ne.jp/Vengineer/","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F70472381\" title=\"UVM\u3067\u3044\u308d\u3044\u308d - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","published":"2016-03-30 05:00:00"}