{"blog_url":"https://vengineer.hatenablog.com/","provider_name":"Hatena Blog","provider_url":"https://hatena.blog","title":"Xilinx\u306eReconfigurable Acceleration","image_url":null,"height":"190","blog_title":"Vengineer\u306e\u5984\u60f3","published":"2016-11-28 04:50:00","version":"1.0","type":"rich","author_url":"https://blog.hatena.ne.jp/Vengineer/","url":"https://vengineer.hatenablog.com/entry/70894437","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F70894437\" title=\"Xilinx\u306eReconfigurable Acceleration - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","categories":["Zynq / Xilinx","#\u305d\u306e\u4ed6\u30b3\u30f3\u30d4\u30e5\u30fc\u30bf"],"description":"@Vengineer\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f Xilinx\u306eReconfigurable Acceleration\u3001\u30d7\u30ec\u30b9\u30ea\u30ea\u30fc\u30b9\u3082\u3002 \u306a\u3093\u304b\u3001\u6628\u65e5\u30d6\u30ed\u30b0\u306b\u66f8\u3044\u305fIntel\u306e\u30c7\u30a3\u30fc\u30d7\u30e9\u30fc\u30cb\u30f3\u30b0\u3068\u4f3c\u3066\u3044\u308b\u3088\u306d\u3002 \u307e\u30fc\u3001FPGA\u3067Deep Neural Network (DNN) \u3092\u5b9f\u88c5\u3057\u3066\u3044\u308b\u306e\u3060\u304b\u3089\u3001\u4f3c\u308b\u3088\u306d\u3002 Intel\u3068\u306e\u9055\u3044\u306f\u3001FFMPEG\u3068SQL\u3082\u3042\u308b\u3068\u3044\u3046\u3053\u3068\u304b\u306a\u3002 Kintex UltraScale\u642d\u8f09\u306eFPGA\u306e\u30dc\u30fc\u30c9\u306b\u3066\u3001\u5bfe\u5fdc\u3059\u308b\u3088\u3046\u3067\u3002 SDAccel\u306b\u3066\u3001OpenCL, C, \u2026","width":"100%","author_name":"Vengineer"}