{"title":"6th RISC-V Workshop Proceedings\u306e\u30d7\u30ec\u30bc\u30f3\u8cc7\u6599\u516c\u958b","blog_url":"https://vengineer.hatenablog.com/","width":"100%","version":"1.0","provider_url":"https://hatena.blog","description":"Vengineer\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f 6th RISC-V Workshop Proceedings\u306e\u30d7\u30ec\u30bc\u30f3\u8cc7\u6599\u304a\u3088\u3073\u8b1b\u6f14\u30d3\u30c7\u30aa\u304c\u516c\u958b\u3055\u308c\u307e\u3057\u305f\u3002 SCR1: open RISC-V compatible MCU core with support \u30bd\u30fc\u30b9\u30b3\u30fc\u30c9\u306f\u3001github\u306b\u3066\u516c\u958b\u3055\u308c\u3066\u3044\u307e\u3059\u3002 \u5f15\u7528 \u30fbRV32I|E[MC] ISA \u30fbMachine privilege mode \u30fb2 to 4 stage pipeline \u30fb32-bit AHB-Lite external int\u2026","blog_title":"Vengineer\u306e\u5984\u60f3","author_url":"https://blog.hatena.ne.jp/Vengineer/","published":"2017-06-09 04:50:00","type":"rich","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F71162496\" title=\"6th RISC-V Workshop Proceedings\u306e\u30d7\u30ec\u30bc\u30f3\u8cc7\u6599\u516c\u958b - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","url":"https://vengineer.hatenablog.com/entry/71162496","image_url":null,"author_name":"Vengineer","height":"190","provider_name":"Hatena Blog","categories":["\u30de\u30eb\u30c1\u30b3\u30a2/RISC-V","#\u305d\u306e\u4ed6\u30b3\u30f3\u30d4\u30e5\u30fc\u30bf"]}