{"url":"https://vengineer.hatenablog.com/entry/71824420","height":"190","version":"1.0","title":"CEVA-BX","provider_name":"Hatena Blog","blog_url":"https://vengineer.hatenablog.com/","width":"100%","provider_url":"https://hatena.blog","author_name":"Vengineer","categories":["\u30c7\u30a3\u30fc\u30d7\u30e9\u30fc\u30cb\u30f3\u30b0/\u6a5f\u68b0\u5b66\u7fd2","#\u305d\u306e\u4ed6\u30b3\u30f3\u30d4\u30e5\u30fc\u30bf"],"description":"@Vengineer\u306e\u622f\u8a00 : Twitter SystemVerilog\u306e\u4e16\u754c\u3078\u3088\u3046\u3053\u305d\u3001\u3059\u3079\u3066\u306f\u3001SystemC v0.9\u516c\u958b\u304b\u3089\u59cb\u307e\u3063\u305f CEVA Announced a New Hybrid DSP/Controller Architecture CEVA-BX : CEVA\u306e\u65b0\u3057\u3044\u3001DSP\u3002hybrid DSP/Contrleer architecture \u30fb11-stage pipeline \u30fb5-way VLIW micro-architecture \u30fbSingle or dual scalar compute engines \u30fbUp to 4.5 CoreMark/MHz sc\u2026","author_url":"https://blog.hatena.ne.jp/Vengineer/","blog_title":"Vengineer\u306e\u5984\u60f3","published":"2019-01-19 04:30:00","html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F71824420\" title=\"CEVA-BX - Vengineer\u306e\u5984\u60f3\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","image_url":null,"type":"rich"}