{"author_url":"https://blog.hatena.ne.jp/shigemk2/","author_name":"shigemk2","url":"https://www.shigemk2.com/entry/2015/02/14/RISC-V_Rocket_Chip%E3%82%92%E5%A3%8A%E3%81%99_%23kernelvm","categories":["\u52c9\u5f37\u4f1a"],"html":"<iframe src=\"https://hatenablog-parts.com/embed?url=https%3A%2F%2Fwww.shigemk2.com%2Fentry%2F2015%2F02%2F14%2FRISC-V_Rocket_Chip%25E3%2582%2592%25E5%25A3%258A%25E3%2581%2599_%2523kernelvm\" title=\"RISC-V Rocket Chip\u3092\u58ca\u3059 #kernelvm - by shigemk2\" class=\"embed-card embed-blogcard\" scrolling=\"no\" frameborder=\"0\" style=\"display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;\"></iframe>","provider_name":"Hatena Blog","description":"@ioriveur UC-berkeley\u304c(\u307e\u305f)\u4f5c\u3063\u305f\u30a2\u30fc\u30ad\u30c6\u30af\u30c1\u30e3 \u4f5c\u308a\u904e\u304e\u3060\u308d\u3046 RV32 RV64 (RV128 in future) Rocket core scala\u3067\u66f8\u304b\u308c\u305fRISC-V\u5b9f\u88c5 Rocket chip\u3068\u306fRISC-V\u306e\u5b9f\u88c5\u3067\u3042\u308brocket Chisel\u3068\u306f ucb-bar/chisel ucb-bar/chisel \u00b7 GitHub code generator to Verilog or C++(emulator) Verilog - Wikipedia \u307f\u3093\u306a\u306fMakefile\u66f8\u3053\u3046\u306d \u52d5\u304b\u306a\u3044 std::bad_alloc Scala\u304c\u81ea\u52d5\u751f\u6210\u3057\u305f\u30b4\u30df\u306e\u3088\u2026","version":"1.0","blog_url":"https://www.shigemk2.com/","blog_title":"by shigemk2","width":"100%","image_url":null,"published":"2015-02-14 21:34:34","height":"190","title":"RISC-V Rocket Chip\u3092\u58ca\u3059 #kernelvm","type":"rich","provider_url":"https://hatena.blog"}