{"image_url":null,"height":"190","categories":["\u30c8\u30d4\u30c3\u30af\u30b9"],"published":"2013-07-20 16:46:12","author_name":"xmldtp","blog_title":"\u30a6\u30a3\u30ea\u30a2\u30e0\u306e\u3044\u305f\u305a\u3089\u306e\u3001\u307e\u3061\u3042\u308b\u304d\u3001\u305f\u3079\u3042\u308b\u304d\u30fcPART2","blog_url":"https://xmldtp.hatenadiary.org/","author_url":"https://blog.hatena.ne.jp/xmldtp/","version":"1.0","type":"rich","url":"https://xmldtp.hatenadiary.org/entry/3a8a7575e5a2031ec674e5ded6daa2a5","title":"\u4eca\u65e5FPGA\u3067\u5b66\u3093\u3060\u3053\u3068\uff08\uff14\uff09","provider_name":"Hatena Blog","description":"\u4eca\u65e5\u3058\u3083\u306a\u3044\u3051\u3069\u3001\u3053\u306e\u524d\u306e\u3064\u3065\u304d\u3067\u3001\u6628\u65e5\u307e\u306a\u3093\u3060\u3053\u3068\u3002 Verilog\u306e\u8d85\u5927\u96d1\u628a\u306a\u96f0\u56f2\u6c17\uff08\u3053\u308c\u3092\u305d\u306e\u307e\u307e\u6253\u3063\u3066\u3082\u52d5\u304b\u306a\u3044\u3002\u3042\u304f\u307e\u3067\u3082\u96f0\u56f2\u6c17\uff09 module MY_MODULE ( input [3:0] A,B, // \u5165\u51fa\u529b\u306e\u5b9a\u7fa9 input CLK, output LED1, output [6:0] CNT ); // \u5185\u90e8\u3067\u4f7f\u3046\u4fe1\u53f7\u306e\u5b9a\u7fa9 reg LED1; // always\u5185\u90e8\u3067\u4f7f\u3046\u5834\u5408\u3001reg\u5ba3\u8a00 wire [4:0] SUM; // \u7d44\u307f\u5408\u308f\u305b\u56de\u8def assign SUM = TASHIZAN(A,B); function [4:0] TASHIZAN; input [3:0] \u2026","width":"100%","provider_url":"https://hatena.blog","html":""}