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  <blog_title>GeekleBoard</blog_title>
  <blog_url>https://ksksue.hatenadiary.org/</blog_url>
  <categories>
    <anon>FPGA</anon>
    <anon>VerilogHDL</anon>
  </categories>
  <description>VerilogHDLで書き始めのテンプレートeclipseのveditor(http://sourceforge.net/projects/veditor/)を入れて Window&gt;Preferences&gt;Verilog/VHDL Editor&gt;Templatesで補完候補に登録しておくと幸せになれる。 /* * module: ${name} * Date:${date} * Author: ${user} * Description * ${cursor} */ /* * Copyright (C) 2013 Keisuke SUZUKI * Licensed under the Apac…</description>
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  <provider_name>Hatena Blog</provider_name>
  <provider_url>https://hatena.blog</provider_url>
  <published>2013-04-21 03:59:10</published>
  <title> VerilogHDLテンプレート</title>
  <type>rich</type>
  <url>https://ksksue.hatenadiary.org/entry/20130421/1366570750</url>
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