shuzo_kino https://blog.hatena.ne.jp/shuzo_kino/ Bye Bye Moore https://shuzo-kino.hateblo.jp/ fpga count: process(clock) begin if rising_edge(clock) then if switch1 = ’1’ then if switch2 = ’1’ then output_signal <= ’1’; else output_signal <= ’0’; end if; end if; end if; end process; 参考もと https://cdn.sparkfun.com/datasheets/Dev/FPGA/IntroToSpartanFPGABook.pdf 190 <iframe src="https://hatenablog-parts.com/embed?url=https%3A%2F%2Fshuzo-kino.hateblo.jp%2Fentry%2F2018%2F05%2F03%2F235452" title="VHDLにおけるIF文 - Bye Bye Moore" class="embed-card embed-blogcard" scrolling="no" frameborder="0" style="display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;"></iframe> Hatena Blog https://hatena.blog 2018-05-03 23:54:52 rich https://shuzo-kino.hateblo.jp/entry/2018/05/03/235452 1.0 100%