SV/UVM based instruction generator for RISC-V processor verification

Vengineer https://blog.hatena.ne.jp/Vengineer/ Vengineerの妄想 https://vengineer.hatenablog.com/ @Vengineerの戯言 : Twitter SystemVerilogの世界へようこそ、すべては、SystemC v0.9公開から始まった見つけた。 github.com ただし、お高いシミュレータが必要。 To be able to run the instruction generator, you need to have an RTL simulator which supports SystemVerilog and UVM 1.2. This generator has been verified with Synopsys VCS, Cadence Incisive/Xce… 190 <iframe src="https://hatenablog-parts.com/embed?url=https%3A%2F%2Fvengineer.hatenablog.com%2Fentry%2F2020%2F02%2F08%2F060000" title="SV/UVM based instruction generator for RISC-V processor verification - Vengineerの妄想" class="embed-card embed-blogcard" scrolling="no" frameborder="0" style="display: block; width: 100%; height: 190px; max-width: 500px; margin: 10px 0px;"></iframe> Hatena Blog https://hatena.blog 2020-02-08 06:00:00 SV/UVM based instruction generator for RISC-V processor verification rich https://vengineer.hatenablog.com/entry/2020/02/08/060000 1.0 100%